An obstacle to the reduction of cell size in DRAM arrays is high channel doping concentrations that are required to achieve the required off current (I.sub.off) objective with existing DRAM cell designs. This problem will be discussed in relation to a common existing DRAM cell design known as MINT (merged isolation node trench), examples of which are found in U.S. Pat. Nos. 5,264,716, 5,360,758, and 5,555,520, and 5,614,431. MINT DRAM cell designs incorporate a buried strap in the storage node trench having an n+ outdiffusion in the single crystal silicon which points in a direction towards the channel of the access transistor.
FIG. 1 is a top view showing the arrangement of elements within a MINT DRAM array 10 which has area of 7 F.sup.2. Although examples of 7 F.sup.2 DRAM cells are known in the art, the particular MINT DRAM array shown in FIGS. 1 and 2 is not admitted to be prior art. As shown in FIG. 1, deep trench storage capacitors 12 are linked to the active area (AA) 14 of a transistor by an outdiffusion from a buried strap 16 formed in the trenches 12. As shown in FIGS. 1 and 2, the gate conductors 18, utilized as wordlines (WLs), are placed in close proximity to the trenches 12. This close placement of the trench 12 to the gate conductor 18 results in overlap of the gate conductor 18 over the outdiffusion 24 from the buried strap 16 as also shown in cross-section in FIG. 2. This effect can cause the length 21 of the transistor channel 19 to be shorter than desired, resulting in lowered threshold voltage V.sub.T, increased transistor off current I.sub.off and increased subthreshold voltage swing. Collectively, these effects can be described as "short channel effects." The short channel effects have an adverse impact on the retention time of the DRAM array. In order to meet the retention time objective, the conventional approach has been to increase doping concentration in the channel region to achieve a higher threshold voltage and reduced off current. However, the increased channel doping concentration results in increases in the junction leakage and substrate sensitivity of the transistor.
The article by T. Hamamoto et al., "Well Concentration: A Novel Scaling Limitation Factor Derived From DRAM Retention Time And Its Modeling," IEDM Technical Digest, Vol. 95, pp. 915-918 (1995) reports that high channel doping concentrations electrically activate defects in the single crystal silicon material of the transistor. As described in that article, crystal defects serve as generation centers for minority carriers which are collected by the storage node diffusion (analogous to the buried strap outdiffusion in the existing MINT DRAM cells). The increased carrier generation, notwithstanding its occurrence in only a small minority of the DRAM array, has a profound impact upon the retention time for the DRAM integrated circuit (IC). High channel doping concentration greatly increases the junction leakage, subthreshold voltage swing and the substrate sensitivity of the IGFET.
The article by T. Ozaki et al. entitled "0.228 um.sup.2 Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Gbit DRAMs," IEDM Digest of Technical Papers, 1995, pp. 661-664 ("the Ozaki et al. Article") describes a proposed DRAM cell design which has dimensions of 6F.sup.2. That proposed cell design is similar to the deep trench DRAM cell designs described above in that the conductive path from the deep trench storage capacitor to the channel of the access transistor is essentially a straight line, except that the design described in the Ozaki et al. Article requires a surface strap rather than a buried strap.
In order to achieve the small cell size, the design described in the Ozaki et al. Article requires the edge of the deep trench storage capacitor to be placed very close to the gate conductor which controls the on-off switching of the transistor channel. The close proximity of the deep trench to the gate conductor leads to short channel effects, which, as described above, lead to lowered threshold voltage and increased transistor off current. In addition, any errors which occur in the positioning of masks which define the deep trench and the gate conductor (even those which are within overlay tolerances) can substantially decrease the channel width and/or prevent the surface strap between the deep trench and the channel from forming. Consequently, existing process tolerances place great obstacles to the implementation of the design described in the Ozaki et al. Article. Because of difficulty in maintaining control over the placement and dimensions of devices within existing process tolerances, the design described in the Ozaki Article results in a high probability of channel shortening effects. High channel doping concentrations, in turn, are required to overcome such short channel effects. However, a high channel doping concentration, as described above, is itself a source of undesirable device degradation.
As the integration density increases, the close proximity between the buried strap and the channel region in existing designs will require ever higher doping concentrations in order to meet I.sub.off and retention time objectives. However, as described above, such higher doping concentrations lead to undesirable device degradation, including increased subthreshold voltage swing, junction leakage, and substrate sensitivity.
One possible way of avoiding the requirement of a higher channel doping concentration would be to increase the physical length of the channel region, which of itself counteracts the above-described short channel effects, and permits a lower channel doping concentration to be used. U.S. Pat. No. 5,614,431 to DeBrosse, which is commonly assigned ("the '431 Patent"), describes one such DRAM cell in which the channel length is increased to 2 F. However, in that design the buried strap and the channel still remain in close proximity. Moreover, the minimum area required by the DRAM cell in the '431 Patent is 8 F.sup.2, in contrast to competing 7 F.sup.2 designs which offer a substantial reduction in area. The increased area occupied by the DRAM cell described in the '431 Patent weighs against the requirement to increase the integration density of the DRAM IC. Finally, the invention herein described can be implemented together with the increased channel length DRAM cell design described in the '431 Patent to provide a DRAM cell having improved operating characteristics by virtue of increased deep trench to gate conductor spacing provided by the invention.
Alternatively, a DRAM cell having larger storage capacitance, such as provided by a larger storage capacitor, could assist in meeting the retention time requirement. However, by existing DRAM designs, this could only be accomplished at expense of increasing the area required by the DRAM cell.
The need to provide increased integration density and to limit the channel doping concentration highlight a need for a DRAM cell design which requires no greater area, but in which the storage capacitor strap is placed further away from the channel of the transistor. In that way, the doping concentration in the channel can be reduced, thereby reducing junction leakage, subthreshold swing and substrate sensitivity, and improving retention time. Alternatively, a DRAM cell structure is needed which provides higher storage capacitance, but without increasing the amount of area occupied by the cell.
Accordingly, it is an object of the invention to provide an arrangement of memory cell elements on a semiconductor substrate in such manner that the distance between the outdiffusion of the storage capacitor strap and the transistor channel is increased without requiring an increase in area.
Another object of the invention is to provide a method of forming storage capacitor trenches within a semiconductor wafer such that the spacing between adjacent trenches is less than the minimum feature size F.
Still another object of the invention is to provide an arrangement of memory cell elements within a semiconductor memory array which accommodates larger storage capacitors without requiring a corresponding increase in the size of each memory cell. A particular object of the invention is to provide an arrangement of memory cell elements within a semiconductor memory array by which larger trench storage capacitors are accommodated by decreasing the spacing between adjacent trench storage capacitors to less than minimum feature size.
A further object of the invention is to provide a method of fabricating elements within a semiconductor memory array by which larger trench storage capacitors are accommodated by decreasing the spacing between adjacent trench storage capacitors to less than minimum feature size.